What will computer chips look like in 2045?

AI demand and semiconductor manufacturing

0:00There's never been as big a shock to the semiconductor industry as the current surge in demand from AI. AI is driving incredible computing demand. Easily 40 to 50% above our maximum capacity, which I've never seen before. Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. But the production of these chips is bottlenecked by tools that Intel buys from their suppliers.

0:31Most famously, ASML's EUV machines. If they don't have the equipment, they can't make the chips here. I spent two days touring Intel's fabs to prepare for these interviews with its leadership. I wanted to understand what it takes to manufacture the world's most advanced chips, and how hardware is shaping the future of AI.

Process development and yield tracking

0:47Okay, I'm joined by Chris Oth, who leads development of all the processes that are currently under manufacturing. The thing I want to understand in more concrete detail is how the development of a new process actually happens. So if 14A is going to come out in three years or two years from now, what is happening from now till then? And I want you to walk me through as much detail as you can, everything from the level of how is the yield improving? What kind of telemetry do you guys look at? What kind of experiments do you guys run? I want to understand what is going to happen over the next two years as concretely as possible.

1:19Yeah, and if we talk about 14A, 14A has actually been in development for about three plus years at this stage. And so quite a bit of free work has been done to get to the stage that it's at right now. And right now we're getting very close to where we're finalizing the process. We're finalizing the tool sets that it will be manufactured on. And we're working on kind of the fine-tuning of each of the process steps. There's about 2,000 steps in the factory that you have to go do. And you need to do really intricate work at each one of those to make sure it's fine-tuned.

1:51It can go into manufacturing. It can run thousands of wafers a week on this process. And it can be repeatable every single time. Right now you might have a certain yield. Walk me through how that increases month over month. So there's a line running at 14A. What happens from now until next month that will result in the yield changing? How do you identify where the defects are? How do you fix that? Yeah, so there's a constant process that we go through in identifying defects. And there's kind of two main ways that we'll identify defects. One is we have inline metrology.

2:21So we have tools that will look at the wafers and say, ah, there's a defect there, there's a defect there, there's a defect there. And then also at end of line, either eat electrical test or we sort and see where the fails are. And we will identify failures. And then we will get analysis on those failures. We'll cross-section it. You were in the TEM lab yesterday. And you saw how you can get cross-sections. You'll get a cross-section of a defect. And from that, you'll be able to say, oh, that defect is between these layers. So it must have come from this section of the flow. Oh, we have inline metrology in that section, which has identified defects.

2:54Those are the defects we need to go after. I think what we've learned is that you don't want to do too much innovation in one node. Because the more innovation that you did, the more complex it becomes. And while you'll be able to get that to work, you need to hit a certain schedule. And that's the schedule that your customer ultimately wants. So having that predictable schedule is a key piece. So you've got to figure out how much innovation you can put in in order to meet the customer's requirements in the timeline that they needed. Intel learned how costly that trade-off can be.

3:24with delays to its 10 nanometer node, whose original target launch date was 2016, but which didn't begin manufacturing until 2018. You know, usually Intel has been the keeper of Moore's law. A new cadence of manufacturing every two years. But their last set of products slipped almost four years. Intel today having its worst day in four months. The stock now down more than 15%. I also want to point out Taiwan Semiconductor up 13% off of Intel's bad news.

Lessons from the 10 nanometer node

3:54Walk me through what lessons you think Intel has learned from 10 nanometer. 10 nanometer was a good example of where we had very aggressive targets. We were doing what was called hyperscaling at the time. So we were scaling much faster than what had been historically done. And in order to do that, we came up with all sorts of innovative ideas and how we could achieve that without new tools because the tools weren't ready. And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that.

4:27Now, at the end of the day, 10 nanometers are great technology. It has world-class yield. It has world-class performance. It has world-class cost. But it took us longer to do that than what we would have liked. And so we've kind of tried to take that learning into future technology nodes and say, hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule. What do you think was the main technology that should have been safe for a future version? EUV was probably the big thing. When we started to define 10 nanometer, what the conclusion was, EUV was not ready.

4:59EUV is extreme ultraviolet lithography. It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chip makers had relied on. The shorter the wavelength, the finer the features that a single exposure can print. But Intel decided this technology wasn't going to be ready in time. TSMC transitioned to EUV much sooner. It put EUV into volume manufacturing in 2019 and ramped it up further on its 5 nanometer node in 2020.

5:32Intel's first EUV process did not reach products until 2023. So TSMC had about four more years of experience with these machines. So yesterday we were at the research lab and we're getting a preview of 2D materials and CFET and erythenium interconnects. And I'm curious about how you decide whether that technology is mature enough for the next node. One thing that did also come out of 10 nanometer is we started to define a set of maturity metrics. And so we use those maturity metrics in a process, which you call phase gate,

6:04where we would say to go from pathfinding into development, these are the criteria that we need to go hit. And there's yield criteria, defect criteria, performance criteria. And we need to hit those in order to move to the next set of the flow. And if there's something that doesn't make that, then it misses that and it goes on to the next technology. And we focus on the items that are ready and we can run and put into a process. Because one of the key things is staying on schedule.

Evolution of transistor architecture

6:28Staying on schedule is hard partly because new transistor designs take decades to mature. Modern trip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history of transistors since has been the progression from two dimensions into three. Each development that Chris goes on to describe, from FinFed to gate all around, is a step in that progression. So it'll help to first look at a basic transistor and how its parts have changed over time. A transistor is basically a switch. When it's turned on, it allows current to flow between its two ends, which are called the source and the drain.

7:05A piece called a gate sits on top of the silicon between the source and the drain. Applying a positive voltage to the gate turns the switch on. Because the positive voltage pulls negatively charged electrons in the silicon beneath up towards the gate. However, a thin layer of insulation stops them from actually reaching the gate. So the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain. This is called the channel.

7:35Remove the voltage and the electrons disperse. The channel disappears and the switch turns off. As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off. We needed a better way to control the channel and prevent current from leaking through. The fix was to give the gate a tighter grip on the channel by touching it from more sides. In the original planar transistor, the gate only touches the channel from the top. The fin-fet transistor squeezes the channel into a thin vertical fin of silicon.

8:09The gate drapes over the fin, so it controls the channel from three sides. The next progression from there was to cover not only the top and the sides of the channel, but also the bottom. This technology is called gate all around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate. But getting gate all around to work required new materials and new manufacturing steps. To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material, which holds the space where the gate will eventually go.

8:42We use a placeholder because the materials in the real gate wouldn't survive the processing that comes after, which involves baking the wafer at around 1,000 degrees Celsius. Once these hot steps are done, chip makers etch away the placeholder, leaving the ribbons suspended. Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-key material, whose purpose is to let the gate pull more strongly on the channel. And then on top of this material, they put the metal of the gate itself. Fin-fet was demonstrated in a lab in 1989 and reached volume production at Intel in 2011.

9:17A gate all-around transistor had been demonstrated a year earlier, in 1988, but Samsung didn't begin producing gate all-around chips until 2022. So these ideas, Fin-fet and gate all-around, were developed around the same time, but they reached production a decade apart. I wanted to ask Chris why it took so long to get to this current gate all-around technology. Maybe you can walk me through then the process of getting into high-volume manufacturing. I want to understand concretely, once you have an idea that, hey, we're going to make the channel smaller, we're going to surround it, all the other problems of material science and figuring out how to not destroy the gate, how did they actually get figured out?

9:57Why does it take so long? Gate all-around is a good example because back in the 90s, we knew of this idea. But we knew there was going to be these problems on how you put this into high-volume manufacturing. And at the same time, there's other things like high-K metal gate, there's strained silicon, there's Fin-fets that are out there. And so it's kind of like, when's the right time to go and tackle those? Well, you don't want to tackle something before you have to. And so if you have these other things that can drive performance, you would go and do that. We went through this path where we did this.

10:28We did strained silicon, high-K metal gate, we did Fin-fets. And then it became, well, we need to do things further. How do we get there? Well, gate all-around is really the ultimate transistor out there. Maybe it's time to go and start tackling some of those issues that you have. And you're right. Now you have to look at how you put high-K metal gate in with gate all-around. So it's that innovation that takes time. Sometimes it's you need new materials. Sometimes it's you need a different tool in order to be able to do some of the things that you need to go do.

10:59And that requires invention from the tool vendors. You have to go to the tool vendors and say, hey, I need a tool that can do X, Y, Z. I need a gas that can deposit this particular material that goes into that. I need a heating chuck that has this characteristic to it. All those things take time. And some of it's iterative where you have to run a gate all-around transition. You say, oh, well, that didn't work. Let me figure out what was wrong with my hypothesis and try it again with some different structure.

Shifting R&D and lithography trade-offs

11:28How has the nature of R&D changed from the era of just making planar transistors smaller and smaller and just getting the benefits of Denard scaling to the world we're in today? Is it just a totally different kind of R&D process where previously you were just like, let's make things smaller, smaller, smaller. Now you do look at all these other facets of performance at the same time. And improvements in size don't come as easily. Walk me through whether there was some crucial change in the R&D process at that point. If you look at the 80s and 90s, yes, it was driven really by Denard scaling, lithography.

11:59We just make things smaller. Transistors got faster. They got more reliable. And it was very predictable cadence. When we started to hit 2000s, what we saw was that's not good enough anymore. We need to do something different. And to me, it became this golden age of innovation. For each technology node, how are you going to provide more scaling? How are you going to provide more performance? And so it drove things like strained silicon. It drove high-K metal gates. It drove FinFETs. It drove gate all around. It drove backside power. These are things that were in the 80s and 90s.

12:32You would be like, oh, no, we're not touching any of that because we just continued to have the same process flow. We just scale it, scale it, scale it. But that's really for somebody like me who's a transistor junkie. It's awesome because now the playbook's open. You can do all sorts of things out there. You can bring in new materials. I mean, just look at the number of materials we used to use in the 90s versus materials today. It's probably gone up 10x. And there's a lot of innovation there. There's atomic layer depositions. I mean, just you're controlling atom by atom this stuff. So it's changed a lot how you approach the process as to before it was try to not change anything to now.

13:08It's like take the sledgehammer and start just just tearing thing up and come up with some new idea. For 14A, Intel is using a new kind of lithography machine, high NA EUV. It uses the same extreme ultraviolet light as today's EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how wide a cone of light the machine's mirrors can focus onto the wafer. The wider the cone you can focus, the smaller the spot that your light can carve. Standard EUV machines have an NA of 0.33.

13:42High NA widens it to 0.55. So high NA can print features about 1.7 times smaller in a single pass. When features are smaller than the lithography machine can print, chip makers have to split the pattern across several passes, each printing a different set of features. The most tightly packed patterns can require two, three, or even four passes. Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects.

14:13High NA machines cost about twice as much, but they can reduce the number of passes that are needed. So the question, which determines whether they justify their higher price, is how much more time they save, and how much they reduce the risk of defects. Now you guys are using high NA UV tools for 14A, whereas TSMC has said that they don't make economical sense yet for them. How do you decide whether the next litho tool is the one that is ready to adopt or not? Yeah, and high NA is a good example of where, because of the architecture of our technology versus TSMCs,

14:50we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side, and that allows you to print that directly with high NA. TSMC has to run very tighter pitches because they don't have backside power, and they can't do that with high NA, so they have to use double-patterning EV. So for them, it's not very helpful. For us, it is very helpful. Now at 14, we've left it as an option, and it's something that we'll have a discussion with the customer on

15:21because there's some value proposition of it. There's some complexity that it adds. Chris is referring to a feature called backside power. A chip has two different kinds of wiring. Power lines deliver electricity to the transistors, and they need to be thick. Signal lines let the transistors talk to each other. They're much thinner, but they need to be spaced apart so that the signal from one wire doesn't interfere with the signal from another. In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel's newest process moves these power lines below the transistors,

15:53to the back of the wafer. This frees up space on top, so the signal lines don't have to be packed as tightly. This change makes high NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with high NA. With backside power, a single high NA pass is enough. Outside companies can now commission Intel to manufacture chips that they've designed. They follow Intel's Process Design Kit, or PDK,

PDKs and foundry business evolution

16:20the menu of what a given process can build, and the rules for building it. Do you need to lock that into your PDK right now for customers who are planning on developing on 14A? It's an option in the PDK today, and we're handling it as a customer-by-customer discussion that we have as to whether or not they want to go down that path or not. So for 18A, there was public reporting that there were delays or issues with the PDK such that some instructions didn't work, and it was difficult for people to use your foundry to build their chips. Tell me about the process of Intel becoming a foundry

16:52and then having a PDK that other customers can use to make whatever chip that they're making as well. There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM, and we've gone to our product teams, and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK-type process. So that's a new process that we've had to go implement on 18A, and 18A started out not having a PDK.

17:22And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they want to see in there. And so we've tried to incorporate that into making sure that, hey, we have a PDK that meets our customers' requirements. And I think that's where we've ended up, is that we're starting to get PDKs that have this. And 14A will have that from the get-go. It has very high-quality PDKs. Again, there's maturity metrics for what is a PDK.5 versus a .9 versus a 1.0.

17:52And we're constantly going through and taking customer feedback and incorporating that into the quality of our PDK. For most of its history, Intel's fabs made only Intel's chips. That could be part of what allowed TSMC to gain an edge. Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines. Basically, all enterprise customers have a shared set of product requirements that you have to meet if you want to even start talking about doing business with them. These are things like SSO,

18:23so employees can log into your app with their company accounts. Or directory sync, so that whenever someone leaves, their access gets shut off automatically. These features are harder to get right than you think. And the risk reward for building them in-house doesn't really make sense. A slightly better version of SSO probably won't accelerate your growth, but a broken one will definitely stunt it. WorkOS gives you access to battle-tested versions of all the most common enterprise features. Things like SSO, SCIM, RBAC, audit logs, and more. WorkOS also has versions of these features that are purpose-built for agents,

18:55so they can log in, grab the right permissions, and take actions within your product. All of these features can be plugged in with just a few lines of code, so you can add them and get started selling to enterprises. OpenAI, Anthropic, and Thinking Machines, as well as more than 3,000 other companies, all rely on WorkOS to meet their enterprise requirements. If you want to join them, go to WorkOS.com and tell them that I sent you. If a butterfly flapped its wings in the 60s, could you imagine a world where Gator all around is not even a word people have heard of,

19:26an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree? And how far down the tech tree do you think things could be totally different? Could it be like we're not even using copper? If you look at, say, transistors and interconnects, I think where we've gotten to, you know, as far as the transistor and Gator all around and it being the ideal transistor structure that I have, I think was somewhat inevitable. As I said, in the 90s, we were already talking about these type of things. Backside power, that one's pretty out there. I think even in the 90s,

19:56the idea that you're going to strip off the entire silicon substrate and put lines on the backside side, you know, that one is probably, you know, something that's a little bit out there. Copper, of course, copper wires are the best, so I don't know how you would end up somewhere else besides copper. But you guys are kind of inevitable. I think for some of the very tightest pitches, you know, I think it's inevitable that you will replace copper. And so that's a good example of where you will have another material that will come in there.

Three-dimensional scaling and thermals

20:24But for the larger lines, I think copper is about where it's at. I think that once you start to do Gator all around transistors and you do backside power, now you start to enter a very different regime because now you see it's not, hey, there's just some substrate and you stack everything on top. Now you've got a transistor, which is floating in interconnect. And you're like, okay, well, why don't I have transistors interconnecting and more transistors, more interconnect? You know, this whole 3D stacking that we now do with just discrete chips that we stack on top of each other.

20:55Now you're like, why can't I just build an entire structure like this? You see it with, you know, memory, NAND, DRAM. You know, they have some incredible 3D structures. NAND already does it. DRAM talks about it. But I think that DRAM inevitably is going to go there too. So a lot of people say, oh, no, we're not going to do this because, hey, we can't do it in the next five years. Well, come on, let's put a larger timescale on this. Let's put 10 years, 20 years in 2045. Do you think you could do it? And now you start to say, oh, yeah, I could see us having some pretty exotic structures at that point.

21:27So we limit ourselves by what we see as possible in the next four years because, you know, as I've always said, you know, when people say, hey, you know, how do you see technology scaling going? Yeah, we have visibility about four years. And then you get out to that four years and you go, yeah, I think there's something we can do another four years out of that. And then you get to that four years and you're like, yeah, I think you can do something. But if you start to talk about 10 years, yeah, it becomes hard to say what it's going to be. Chris's idea of building upwards could start with the transistors themselves. Chips use two types of transistors called N-type and P-type, which work the same way, but with the charges reversed.

22:00Nearly every circuit is built by pairing them up. Today, chip makers build them side by side. The next step is to stack them directly on top of each other in order to save space. In principle, that fits twice as many transistors into the same area. This design is called a CFET, short for Complementary Field Effect Transistor. But every extra layer adds manufacturing steps and cost and also leads to heat building up that doesn't have a clear way to escape. Because logic consumes more power than memory,

22:30you can't do stacks of DRAM that make HBM or 3D NAND as easily with logic because of the heat issue. Is that the fundamental issue then over the long run? Is how you both dissipate it? Thermals, yeah. So there's three things that you have when you try to say, hey, what limits compute? Okay, it's how fast can you do the switch? So the frequency of the device. How much power does it take in order to do that switch? So the power efficiency of it. And the second one is, how do you dissipate the heat that was generated by doing that switch?

23:02And that's the thermals piece of it. And I think the thermals piece is, and these are not new problems. You can go back 20 years and you can see articles on these three things. And so the question is, yeah, thermals, how do you deal with that? Particularly when you start to talk about these 3D type devices. I think that there is a need for that sort of system level analysis and simulation tools. I think we're at its infancy because we've just started to look at this. But it is a limiter and it will be a limiter. But, you know, again, these are problems that we can go solve.

23:33The problems respond to work, but engineering time is finite and so are the wafers for experiments. Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node. I sat in on one of Intel's Hot Topics meetings where those decisions get made.

Hot topics and urgent factory decisions

23:50Okay, I'm here with Kevin Fisher, who was laying down the law this morning at the Hot Topics meeting where you guys were discussing how you're improving 18A and 18AP technologies. And people would come to you with these different experiments they were running, different ideas they had for improving yield and for improving performance. And then you and your integration engineers would tell them what data you needed, tell them how they should proceed, tell them how you think you can move things faster. I want people to have a sense of the culture of these meetings. And so one thing that I found striking is just that there's, you know,

24:20this is bottlenecking your most advanced node. You want to progress to happen fast. And so you kind of lay down the hammer. I would say the average engineer doesn't understand the stakes or the urgency of how this is going to impact, you know, Intel's bottom line, how it's going to impact our customer. They just have no visibility to those issues, right? So they will typically have a certain set of criteria

24:50that they want to go capture. They'll hit boundaries of, you know, I asked for something and someone said no. And, you know, I'm done. I can't, I can't, I guess I can't have this thing that I asked for. One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you've waited too long. It's already too late. So a lot of what I end up doing in those meetings is I decide how much risk we're going to take on a certain decision or not take on a certain decision.

25:22And you need to say, look, do we go now? Do we start risking production? Because you're risking, you know, the bottom line. You're risking revenue. I'm worried you're going to put me in the light of being an ogre because I'm putting the hammer down on people. That's a great reputation to have. It's really conveying urgency. Yes. Every day counts. Yeah. Can you walk me through a particular issue that might come up? Well, one of the examples you saw this morning, which is epi nodules. Epi is short for epitaxy,

25:52which means growing new material on top of an existing one. Chip makers flow gases over a heated wafer and the gases leave atoms on its surface. The crystal structure of the material underneath acts as a template. Each new atom lines up with the atoms below it and the new layer continues the same crystal. Chip makers use epitaxy at several stages of making a chip. In the step Kevin describes, they use it to grow the source and the drain as small crystals on either side of the gate. So during the deposition of our epitaxy,

26:22we get abnormal growth, like a tumor. Yeah. Right? It's going super fast. Yeah. And that causes problems because one epi will short to the wrong epi and you get transistors not working. And then you've got to narrow it down to how are you going to fix it? For the past decade, Intel's chips have had this feature called processor trace. When you turn it on, it starts recording all the code your program runs and it captures enough detail that it can go back later and reconstruct every single function call. Most companies don't need that level of detail,

26:54but Jane Street does. They need to investigate specific fleeting moments in their trading systems. Things like a delayed response to a network packet. Those events tend to be too brief for most debugging tools to catch. So when one of Jane Street's engineers noticed processor trace, he started playing around with it. And then he and a summer intern turned that exploration into a new tool called MagicTrace. MagicTrace leverages the output from processor trace to give Jane Street a history of every function call leading up to a specific moment of interest.

27:24This project was completely bottoms up. It started just as something that one engineer thought would be valuable. And now, traders and developers across Jane Street use MagicTrace every single day. If you want to work somewhere where you're trusted to pursue the ideas that you think matter most, Jane Street is hiring researchers and engineers. Go to janestreet.com slash thorkash to learn more. One of the pieces that you observed this morning was a special clean that we were looking at, which would eliminate the nodule, right? So the nodule would deposit and then we'd get rid of it.

27:56Some of the other discussion was, well, the source of the nodule, get rid of the source of the nodule, right? So how do you decide what, there's some issue, how do you decide what the source of it is? For the most part, we work highly parallel, right? So how do you decide? It's not always evident what the easiest way to fix the problem is. So you work on all the potential fixes. And sometimes it's not the one you expect first. Once we've identified it as a primary problem for the technology, that's where this Hot Topics meeting gets involved.

28:26And that's how we align the resources into those engineering teams so that we can accelerate the work. You said that there's like some fast strike process where wafers can move through faster if they're bottlenecking some experiment. So we have a tiered system of what we call hotboxes in the factory. And every grade of hotbox goes a little bit faster. And it's just how the factory prioritizes that particular lot, that block of silicon that's running through the factory. So our highest grade of hotbox,

28:57hotbox one, races through the factory. It gets priority at every single tool, but it's a drag on the entire factory. If you had a factory person in here, they don't like playing that car because you're ending up using the tools inefficiently so that you can go super, super fast. Think of it as a highway and you set aside that one lane for the carpool, right, which everyone could use, but you're saying, okay, it's just the carpool. That's our hotbox one. Yeah. Right? Everyone clear out of that lane except for that one experiment.

29:28And that one experiment races down the highway. Kevin's job is deciding what goes on the production line now. But the day before, I went to Intel's research lab with Jack Cavalieros to see ideas that aren't ready for the node yet. We started with wiring. A transistor is only useful once it's connected to others. And on a modern chip, that takes more than a dozen layers of metal wires stacked above the transistors called interconnect. These wires are made of copper. And as they shrink, copper starts to run into trouble. Intel is exploring a replacement,

30:00ruthenium. Ruthenium has higher resistivity. So why are you guys exploring ruthenium for the future? So interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. For example, copper requires typically a liner in order to deposit the copper to fill those lines. Ruthenium is very different in that regard because it's a material that we can actually etch. And as such, by etching it, we don't need that liner. So now you scale those very fine dimensions. And if you can trade off

30:31that resistive liner with no liner, ruthenium starts to win. So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper. And that's roughly in the 20 nanometer pitch range, which means if you can imagine half of the pitch is your metal line and the other half is the dielectric that isolates. So what is the liner? The liner is, think of it almost like a glue layer or a transition layer that we need in order to deposit

31:01the copper and have it stick and make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other. But every time you deposit copper, you've always had a liner underneath it. And in the past, that liner may have been a significant portion of the entirety of that conduction path. But over time, we've scaled it, made it thinner, and so copper comes back into play as a contender. One thing I'd be curious about to know is how you decide that a technology is mature and ready

31:33for high-volume manufacturing. So with 10 nanometer, you're mentioning you guys moved around from copper to cobalt and there were

Material selection and short-loop learning

31:41potential issues with that. How do you decide that this technology is going to work at scale? So the integration of these materials into such a complex system as the transistor ecosystem involves many, many different components. The scalability is one part, but its ability to integrate is another. At the time we made a decision for cobalt, it was the forerunner. The results were stronger at the time. But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with,

32:12we find solutions down the road that may bring copper back in line as being the stronger of the two. And that's exactly what happens. Every technology that we go through, we will evaluate multiple options. And as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision. And the leading option at the time was cobalt. Now it's copper again. And perhaps in the future, it'll be ruthenium. I'd love to get your thoughts

32:42on CFET, basically stacking the transistors on top of each other. What is progress like there? Can we keep making more and more layers? Is it just two? Can we go three, four? How high can you get? Yeah, so that evaluation of CFET is currently underway, not just by us, by our competition. Labs externally are looking at it. It is the ultimate in stackability. We're taking transistors that had to be compressed more and more. And we're relaxing that in some ways because we're going to stack

33:13them on top of each other. But the act of stacking does not mean that they're not interconnected. What used to be connections on the top or even on the bottom as you've seen from our press release now has to go vertically in between the transistors. And that's a new challenge because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult. So it's not as straightforward as stacking the transistors because you still have to think about interconnecting them. Is the issue there the etch to get that deep hole? Aspect ratio for the etches

33:44is a big part of it. We're working with our vendors to evolve on that. But it's also what you fill those very tiny spaces with because filling can sometimes leave air gaps or holes that never really fill. And that's not ideal. I assume there's a version of CFET that works inside this lab. What is the kind of wafer or process or whatever that is working right now? Then what's the next step? What's the next step? What's the next step until it's inside the full high volume process? Part of the process of evolving these technologies,

34:15especially something more complex like an architecture, not just a basic chemistry or a material, but the full architecture like CFET is that we have to make short loop vehicles that can give us faster turnaround. The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them. So we take advantage of short loop vehicles that can give us, you know,

34:45electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps. And once we've resolved them, then we combine them into a more complex test vehicle. So what you would find in here is something very simple. You might be making a diode. You might be making a capacitor, which are components of the transistor. And as those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself.

35:17So in the CFET example, you might not choose to do four ribbons on top of four ribbons. You might just choose to do one-on-one because naturally the aspect ratio of dealing with something that much taller becomes more and more challenging. So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS. And that simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect. But are the feature sizes here

35:48as small as they will be eventually, or are the feature sizes bigger as well? Oh, absolutely. In some cases, at least as small. For example, you know, you've heard of 2D materials, these transition layer dicot collagenides as they're called. They're very, very thin materials. They're essentially one monolayer of atoms that we deal with. Those depositions can happen in this lab. We can evaluate those films in terms of conductivity, our ability to contact them, our ability to modulate

36:19that conductivity, which is what the transistor does. So yes, we do have the ability to not only deposit films that are very small and thin to the atomic scale, but also print very small features. We have EUV technology that can, or e-beam technology that can allow us to print very small features similar to what we will eventually make in production. So I guess I don't understand intuitively, lacking the context

36:50in this process, why that, you have the features that are as small for working CFET right now. Yes. Why will it take 10 years for it to be in my phone? What is, I understand that it's like a process, but why is it such a long process? The answer is slightly different when you're dealing with an architecture like CFET versus a novel material. Materials have, of course, the challenges of being deposited, etched, removed, their compatibility with other layers above and below.

37:21All those things have to be researched first before you put them in a production line. an architecture may seem like a simple evolution. Oh, you're making nanoribbon transistors next to each other. What's wrong with just stacking them? But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, and the technology may simply not be ready yet. But if you've already made it here, there's a version of the technology that's ready, right? Correct. So we've made a simplified version

37:52that may not be an advantage over our current side-by-side technology of nanoribbons. But we need to evolve it to make it maybe two nanoribbons or to add the right type of metals and dielectrics in order to extract the maximum performance out of that device. Got it. So it's like a long tail of... There's a thousand different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.

38:22Where do the ideas tend to fail? So like you have like 20 ideas that are like 2D materials. What is the kind of way in which you're like this is actually not worth pursuing further? Sometimes the idea becomes something that we discover fundamentals about the material that will be incompatible with the rest of the processing that we do. At first, you know, the first level of experiments may simply be very simple depositions and you say, okay, I can deposit the film, I can look at it, I can measure

38:52it,